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hy57v641620hg 4 banks x 1m x 16b it synchronous dram this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pa tent licenses are implied. rev. 0.8/dec. 02 1 description the hynix hy57v641620hg is a 67,108,864-bit cmos synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. hy 57v641620hg is organized as 4banks of 1,048,576x16. hy57v641620hg is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are sy nchro- nized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all inpu t and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of cons ecutive read or write cycles in itiated by a single control command (burst length of 1,2,4,8 or full pa ge), and the burst count sequenc e(sequential or interleave). a b urst of read or write cycles in progress can be terminated by a burst termi nate command or can be interrupt ed and replaced by a new bur st read or write command on any cycle. (this pi pelined design is not restricted by a `2n` rule.) features ? single 3.3 0.3v power supply note) ? all device pins are compatible with lvttl interface ? jedec standard 400mil 54pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm or ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information note : vdd(min) of hy57v641620hg(l)t-5/55/6 is 3.135v part no. clock frequency power organization interface package hy57v641620hgt-5/55/6/7 200/183/166/143mhz normal 4banks x 1mbits x16 lvttl 400mil 54pin tsop ii hy57v641620hgt-k 133mhz hy57v641620hgt-h 133mhz hy57v641620hgt-8 125mhz hy57v641620hgt-p 100mhz hy57v641620hgt-s 100mhz hy57v641620hglt-5/55/6/7 200/183/166/143mhz low power hy57v641620hglt-k 133mhz hy57v641620hglt-h 133mhz hy57v641620hglt-8 125mhz hy57v641620hglt-p 100mhz hy57v641620hglt-s 100mhz
hy57v641620hg rev. 0.8/dec. 02 2 pin configuration pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0,ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details ldqm, udqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for in ternal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd 54pin tsop ii 400mil x 875mil 0.8mm pin pitch
hy57v641620hg rev. 0.8/dec. 02 3 functional block diagram 1mbit x 4banks x 16 i/o synchronous dram x decoders state machine a0 a1 a11 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 1mx16 bank 3 x decoders x decoders memory cell array y decoders x decoders 1mx16 bank 0 1mx16 bank 1 1mx16 bank 2
hy57v641620hg rev. 0.8/dec. 02 4 absolute maximum ratings note : operation at above absolute maximum rati ng can adversely affe ct device reliability dc operating condition (ta=0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.vdd(min) of hy57v641620hg(l)t-5/55/6 is 3.135v 3.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration 4.v il (min) is acceptable -2.0v ac pulse width with 3ns of duration ac operating condition (ta=0 to 70 c , v dd =3.3 0.3v note2 , v ss =0v) note : 1. output load to measure access time is equivalent to two ttl gates and one capacitor (50pf) for details, refer to ac/dc output circuit 2.vdd(min) of hy57v641620hg(l)t-5/55/6 is 3.135v parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1,2 input high voltage v ih 2.0 3.0 v ddq + 2.0 v 1,3 input low voltage v il v ssq - 2.0 0 0.8 v 1,4 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
hy57v641620hg rev. 0.8/dec. 02 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v note3 ) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 parameter pin symbol min max unit input capacitance clk c i1 24pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 5 pf data input / output capacitance dq0 ~ dq15 c i/o 26.5pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol = +4ma vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
hy57v641620hg rev. 0.8/dec. 02 6 dc characteristics ii (ta=0 to 70 c , v dd =3.3 0.3v note5 , v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specif ied values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.hy57v641620hgt-6/7/k/h/p/s 4.hy57v641620hglt-6/7/k/h/p/s parameter symbol test condition speed unit note -5 -55 -6 -7 -k -h -8 -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 1009590858585808080ma1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 2ma i dd2ps cke v il (max), t ck = 2ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd - 0.2v or 0.2v 15 ma i dd2ns cke v ih (min), t ck = input signals are stable. 12 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 6ma i dd3ps cke v il (max), t ck = 5ma active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd - 0.2v or 0.2v 30 ma i dd3ns cke v ih (min), t ck = input signals are stable. 20 ma burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 170 160 150 150 150 150 120 120 120 ma 1 cl=2 na na na na 120 ma auto refresh current i dd5 t rrc t rrc (min), all banks active 160 ma 2 self refresh current i dd6 cke 0.2v 1ma3 400 ua 4
hy57v641620hg rev. 0.8/dec. 02 7 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate parameter symbol -5 -55 -6 -7 -k -h -8 -p -s unit note min max min max min max min max min max min max min max min max min max system clock cycle time cas latency = 3 tck3 5 1000 5.5 1000 6 100 0 7 1000 7.5 1000 7.5 1000 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 10 10 10 7.5 10 10 10 12 ns clock high pulse width tchw 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 4.5 - 5 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns 2 cas latency = 2 tac2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns data-out hold time toh 1.5 - 2 - 2 - 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns data-input setup time tds 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 data-input hold time tdh 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 address setup time tas 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 address hold time tah 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 cke setup time tcks 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 cke hold time tckh 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 command setup time tcs 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 command hold time tch 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 clk to data output in low z-time tolz 1 - 1 - 1 - 1.5 - 1.5 - 1.5 - 1 - 1 - 2 - ns clk to data output in high z-time cas latency = 3 tohz3 5.0 5.4 5.4 5.4 5.4 5.4 36 66 ns cas latency = 2 tohz2 36 ns
hy57v641620hg rev. 0.8/dec. 02 8 ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbo l -5 -55 -6 -7 -k -h -8 -p -s unit note min max min max min max min max min max min max min max min max min max ras cycle time operation t rc 55 - 55 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns auto refresh t rrc 60 - 60 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns ras to cas delay t rcd 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns ras active time t ras 38.5 100k 38.5 100k 42 100 k 42 120k 45 120k 45 120k 48 100 k 50 120k 50 120k ns ras precharge time t rp 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns ras to ras bank active delay t rrd 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns cas to cas delay t ccd 1-1-1-1-1-1-1-1-1-clk write command to data-in delay t wtl 0-0-0-0-0-0-0-0-0-clk data-in to precharge command t dpl 2-2-2-1-1-1-2-1-1-clk data-in to active command t dal 5-5-5-4-4-4-5-3-3-clk dqm to data-out hi-z t dqz 2-2-2-2-2-2-2-2-2-clk dqm to data-in mask t dqm 0-0-0-0-0-0-0-0-0-clk mrs to new command t mrd 2-2-2-1-1-1-2-1-1-clk precharge to data output hi-z cas latency = 3 t proz 3 3-3-3-3-3-3-3-3-3-clk cas latency = 2 t proz 2 2-2-2-2-2-2-2-2-2-clk power down exit time t pde 1-1-1-1-1-1-1-1-1-clk self refresh exit time t sre 1-1-1-1-1-1-1-1-1-clk1 refresh time t ref - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
hy57v641620hg rev. 0.8/dec. 02 9 device operatin g option table hy57v641620hg(l)t-5 hy57v641620hg(l)t-55 hy57v641620hg(l)t-6 hy57v641620hg(l)t-7 hy57v641620hg(l)t-k hy57v641620hg(l)t-h cas latency trcd tras trc trp tac toh 200mhz(5ns) 3clks 3clks 7clks 10clks 3clks 4.5ns 1.5ns 183mhz(5.5ns) 3clks 3clks 7clks 10clks 3clks 5.0ns 2ns 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2ns cas latency trcd tras trc trp tac toh 183mhz(5.5ns) 3clks 3clks 7clks 10clks 3clks 5.0ns 2ns 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2ns 143mhz(7ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.7ns cas latency trcd tras trc trp tac toh 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 133mhz(7.5ns) 2clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns cas latency trcd tras trc trp tac toh 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 2clks 2clks 6clks 8clks 2clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns
hy57v641620hg 4 banks x 1m x 16b it synchronous dram this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pa tent licenses are implied. rev. 0.8/dec. 02 10 hy57v641620hg(l)t-8 hy57v641620hg(l)t-p hy57v641620hg(l)t-s cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 7clks 10clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 3clks 6ns 3ns 83mhz(12ns) 3clks 3clks 6clks 9clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
hy57v641620hg rev. 0.8/dec. 02 11 command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 pin high (other pins op code) self refresh 1 entry h l l l l h x x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
hy57v641620hg rev. 0.8/dec. 02 12 package information 400mil 54pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)bsc 0.400(0.016) 0.300(0.012) unit : mm(inch) 0.150(0.0059) 0.050(0.0020)

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